內建式類比數位/數位類比轉換器線性度之自我測試

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姓名

陳俊宏(Jun-Hong Chen ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

內建式類比數位/數位類比轉換器線性度之自我測試
(BIST for ADCs/DACs Linearity Testing)

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摘要(中)

在這篇論文中，我們提出了一個新的內建式自我測試的方法，可以用來測試在同一個晶片上之類比數位與數位類比轉換器之線性度。內建在同一個晶片上之數位訊號處理及微處理單元亦是可以用來計算測試結果的測試資源，因此我們提出的這個架構也可以充分的利用這些資源。為了不要因為外加的測試電路來降低整個系統的效能，我們的測試電路加越少越好。在處理測試的資料方面，超量取樣的統計方式在這裡可以有效的被運用。我們所提出的測試方法與機制亦是易於控制和分析的。

摘要(英)

In this thesis, a new test methodology of BIST for on-chip ADC-DAC pair linearity testing is proposed. The on-chip digital signal processing unit and micro processing unit are used as test sources for calculating the test results. Hence, the on-chip test resources are fully used for our testing methodology. The test circuits are added as few as possible to prevent performance degradation of the overall system. To reduce the influence of system noise, the statistical methodology of oversampling is used. The proposed BIST scheme is ease of control and analysis.

關鍵字(中)

★ 內建式自我測式
★ 數位類比轉換器
★ 混合信號測試
★ 非線性度
★ 類比數位轉換器

關鍵字(英)

★ ADC
★ BIST
★ DAC
★ mixed-signal testing
★ nonlinearity
★ testing

論文目次

1. Introduction
1.1 Motivation
1.2 ADC/DAC Testing Methodologies Overview
1.3 Thesis Organization
2. Survey of ADC/DAC Testing Methodologies
2.1 Introduction
2.2 ADC Testing Methodologies
2.2.1 Static Test Method
2.2.2 Dynamic Test Method: Histogram Testing
2.2.3 Dynamic Test Method: FFT Testing
2.3 DAC Testing Methodologies
2.4 BIST for DAC-ADC Pair
3. Proposed Methodology for on-chip ADCs/DACs Testing
3.1 Introduction
3.2 BIST Structure for On-Chip ADCs/DACs Testing
3.3 Testing Strategy and Consideration
3.4 Simulation Results
3.4.1 Phase 1: Deriving the output codes of the
reference voltages
3.4.2 Phase 2: Time constant determination and ADC INL
3.4.3 Phase 3: Deriving integral nonlinearity of the DAC
4. Hareware Testing Results
4.1 Introduction
4.2 Test Environment
4.3 Test Results
4.3.1 Phase 1 test results
4.3.2 Phase 2 test results
4.3.3 Phase 3 test result
5. Conclusions

參考文獻

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指導教授

蘇朝琴(Chauchin Su)

審核日期

2001-7-12

推文